View 87C196JV_4989824.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

87C196JV 20 mhz advanced 16-bit chmos microcontroller automotive production datasheet product features n C 40c to + 125c ambient n powerdown and idle modes n high performance chmos 16-bit cpu n 48 kbytes of on-chip eprom n up to 1.5 kbyte of on-chip register ram n 512 bytes of additional ram (code ram) n register-register architecture n six channel/10-bit a/d with sample/hold n programmable a/d conversion and s/h times n 35 prioritized interrupt sources n up to seven 8-bit (56) i/o ports n full duplex serial i/o port n dedicated baud rate generator n 20 mhz operating frequency n high speed peripheral transaction server (pts) n two 16-bit software timers n six high speed capture/compare (epa) n two flexible 16-bit timer/counters n full duplex synchronous serial i/o port (ssio) n flexible 8-/16-bit external bus n windowing allows 8-bit addressing to some 16-bit addresses n 1.4 s 16 x 16 multiply n 2.4 s 32/16 divide n 52-pin plcc package n oscillator fail detect order no: 272580-004 january 13, 1998 notice: this document contains information on products in full production. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design.
87C196JV - automotive ii production datasheet information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the 87C196JV - automotive may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation po box 5937 denver co 80217-9808 call 1-800-548-4725 copyright ? intel corporation 7/8/97 *third-party brands and names are the property of their respective owners.
production datasheet iii 87C196JV - automotive contents 1.0 introduction .....................................................................................................1 2.0 pin descriptions .............................................................................................3 3.0 electrical characteristics .................................................................4 3.1 dc characteristics ................................................................................ 4 3.2 ac characteristics ................................................................................ 6 3.2.1 test conditions .................................................................................. 6 3.2.2 explanation of ac symbols................................................................ 9 3.3 eprom specifications .......................................................................... 10 3.3.1 ac eprom programming characteristics....................................... 10 3.3.2 eprom programming waveforms .................................................. 11 3.4 a/d converter specifications.......................................................... 12 3.5 ac characteristics - serial port - shift register mode........................ 14 3.5.1 52-lead device design considerations ........................................... 15 3.5.2 87C196JV - automotive errata......................................................... 16 3.5.3 87c196jr/jq d-step to 87C196JV - automotive a-step design consider- ations16 3.5.4 87c196jr/jq c-step to jv a-step design considerations ............. 17 3.5.5 87c196jt to 87C196JV design considerations .............................. 20 3.5.6 memory map for jv .......................................................................... 21 4.0 datasheet revision history ................................................................22
87C196JV - automotive iv production datasheet figures 1 87C196JV - automotive block diagram ...........................................................1 2 87C196JV - automotive family nomenclature ................................................2 3 package diagram.............................................................................................2 4 system bus timing ..........................................................................................7 5 external clock drive waveforms .....................................................................8 6 input/output test conditions ...........................................................................8 7 float test conditions .......................................................................................9 8 slave programming mode data program mode with single program pulse .11 9 slave programming mode in word dump or data verify mode with auto increment .......................................................................................11 10 slave programming mode timing in data program mode with repeated program pulse and auto increment .......................................12 11 waveform - serial port - shift register mode 0 .............................................14 tables 1 pin descriptions ...............................................................................................3 2 dc characteristics (under listed operating conditions).................................4 3 ac characteristics (over specified operating conditions)..............................6 4 external clock drive.........................................................................................8 5 thermal characteristics ...................................................................................9 6 explanation of ac symbols..............................................................................9 7 ac eprom programming characteristics.....................................................10 8 dc eprom programming characteristics ....................................................10 9 a/d operating conditions ..............................................................................12 10 a/d characteristics ........................................................................................13 11 serial port timing - shift register mode........................................................14
production datasheet 1 87C196JV - automotive 1.0 introduction the 87C196JV - automotive a-step (jv-a), is a member of the mcs ? 96 microcontroller family. this device is a memory scalar of the 87c196jt a-step (jt-a) and is designed for strict functional and electrical compatibility. the 87C196JV - automotive has the highest 52-lead memory density of the mcs 96 microcontroller family, with 48k of on-chip eprom, 1.5 k of on-chip register ram, and 512 bytes of additional ram (code ram). the high memory integration of the 87C196JV - automotive supports high-functionality in a low pin-count package and the use of the high level programming language c. the mcs 96 microcontroller family members are all high-performance microcontrollers with a 16-bit cpu. the 87C196JV - automotive is composed of the high-speed (20 mhz) core as well as the following peripherals: 48 kbytes of program eprom, up to 1.5 kbyte of register ram, 512 bytes of code ram (16-bit addressing modes) with the ability to execute from this ram space, a 6 channel-10-bit/ 3 lsb analog to digital converter with programmable s/h times with conversion times 15 s at 20 mhz, an asynchronous/synchronous serial i/o port (8096 compatible) with a dedicated 16-bit baud rate generator, an additional synchronous serial i/o port with full duplex master/slave transceivers, a flexible timer/counter structure with prescaler, cascading, and quadrature capabilities, 6 modularized multiplexed high speed i/o for capture and compare (called event processor array) with 250 ns resolution and double buffered inputs, a sophisticated prioritized interrupt structure with programmable peripheral transaction server (pts). the pts has several channel modes, including single/burst block transfers from any memory location to any memory location, a pwm and pwm toggle mode to be used in conjunction with the epa, and an a/d scan mode. additional sfr space is allocated for the epa and can be windowed into the lower register ram area. figure 1. 87C196JV - automotive block diagram a5865-01 clock generator port0 epa0 - 3,8,9 ach2 - 7 port1 t2clk t2dir port2 port3 port4 port5 sc0 sc1 sd0 sd1 txd rxd port6 i/o ports timer 1 & 2 register ram a/d converter (10-bit) [6 channels] peripheral transaction server (pts) power and gnd alu xtal2 control signals addr/ data bus xtal1 16 512 bytes code ram on-chip rom/eprom (optional) event processor array (epa) programmable interrupt controller serial i/o (uart & ssio) v cc v ss v ss v ss v ref angnd 16 memory controller with prefetch queue
87C196JV - automotive 2 production datasheet figure 2. 87C196JV - automotive family nomenclature figure 3. package diagram a4576-01 an 87 c v j 196 0 = romless 3 = masked rom 7 = eprom, otp, qrom product designation product family chmos technology program memory options: j = cerquad n = plcc (plastic leaded chip carrier) package type options: a = -40 ? c to +125 ? c ambient with intel standard burn-in temperature and burn-in options: a4575-01 p6.1 / epa9 p6.0 / epa8 p1.0 / epa0 / t2clk p1.1 / epa1 p1.2 / epa2 / t2dir p1.3 / epa3 v ref angnd p0.7 / ach7 p0.6 / ach6 p0.5 / ach5 p0.4 / ach4 p0.3 / ach3 ad15 / p4.7 wr# / wrl# / p5.2 rd# / p5.3 v pp v ss ale / adv# / p5.0 v ss xtal1 xtal2 p6.7 / sd1 p6.6 / sc1 p6.5 / sd0 p6.4 / sc0 ad14 / p4.6 ad13 / p4.5 ad12 / p4.4 ad11 / p4.3 ad10 / p4.2 ad9 / p4.1 ad8 / p4.0 ad7 / p3.7 ad6 / p3.6 ad5 / p3.5 ad4 / p3.4 ad3 / p3.3 ad2 / p3.2 46 45 44 43 42 41 40 39 38 37 36 35 34 87C196JV 52-pin plcc and cerquad view of component as mounted on pc board 8 9 10 11 12 13 14 15 16 17 18 19 20 ad1 / p3.1 ad0 / p3.0 reset# ea# v ss v cc p2.0 / txd p2.1 / rxd p2.2 / extint p2.4 p2.6 p2.7 / clkout p0.2 / ach2 21 22 23 24 25 26 27 28 29 30 31 32 33 7 6 5 4 3 2 1 52 51 50 49 48 47
production datasheet 3 87C196JV - automotive 2.0 pin descriptions table 1. pin descriptions name description v cc main supply voltage (+5 v). v ss digital circuit ground (0 v). there are three v ss pins, all of which must be connected to a single ground plane. v ref reference for the a/d converter (+5 v). v ref is also the supply voltage to the analog portion of the a/d converter and the logic used to read port 0. must be connected for a/d and port 0 to function. v pp programming voltage for the eprom parts. it should be +12.5 v for programming. it is also the timing pin for the return from powerdown circuit. connect this pin with a 1 f capacitor to v ss and a 1 m w resistor to v cc . if this function is not used, v pp may be tied to v cc . angnd reference ground for the a/d converter. must be held at nominally the same potential as v ss . xtal1 input of the oscillator inverter and the internal clock generator. xtal2 output of the oscillator inverter. p2.7/clkout output of the internal clock generator. the frequency is 1/2 the oscillator frequency. it has a 50% duty cycle. also lsio pin. reset# reset input to the chip. input low for at least 16 state times resets the chip. the subsequent low-to-high transition resynchronizes clkout and commences a 10-state time sequence in which the psw is cleared, bytes are read from 2018h and 201ah loading the ccbs, and a jump to location 2080h is executed. input high for normal operation. reset# has an internal pullup. ea# input for memory select (external access). ea# equal to a high causes memory accesses to locations 2000h through 5fffh to be directed to on-chip eprom/rom. ea# equal to a low causes accesses to these locations to be directed to off- chip memory. ea# = +12.5 v causes execution to begin in the programming mode. ea# latched at reset. p5.0/ale/adv# address latch enable or address valid output, as selected by ccr. both pin options provide a latch to demultiplex the address from the address/data bus. when the pin is adv#, it goes inactive (high) at the end of the bus cycle. adv# can be used as a chip select for external memory. ale/adv# is active only during external memory accesses. also lsio when not used as ale. p5.3/rd# read signal output to external memory. rd# is active only during external memory reads or lsio when not used as rd#. p5.2/wr#/wrl# write and write low output to external memory, as selected by the ccr, wr# goes low for every external write, while wrl# goes low only for external writes where an even byte is being written. wr#/wrl# is active during external memory writes. also an lsio pin when not used as wr#/wrl#. p1.0/t2clk dual-function i/o pin. primary function is that of a bidirectional i/o pin, however it may also be used as a timer2 clock input. the timer2 increments or decrements on both positive and negative edges of this pin. p1.2/t2dir dual-function i/o pin. primary function is that of a bidirectional i/o pin, however it may also be used as a timer2 direction input. the timer2 increments when this pin is high and decrements when this pin is low. port1/epa0-3 p6.0-6.1/epa8-9 dual-function i/o port pins. primary function is that of bidirectional i/o. system function is that of high speed capture and compare. epa0 and epa2 have yet another function of t2clk and t2dir of the timer2 timer/counter. port0/ach2-7 6-bit high impedance input-only port. these pins can be used as digital inputs and/or as analog inputs to the on-chip a/d converter. these pins are also used as inputs to eprom parts to select the programming mode. p6.4-6.7/ssio dual-function i/o ports that have a system function as synchronous serial i/o. two pins are clocks and two pins are data, providing full duplex capability. port2 8-bit multi-functional port. all of its pins are shared with other functions. port3 and 4 8-bit bidirectional i/o ports with open drain outputs. these pins are shared with the multiplexed address/data bus which has strong internal pullups.
87C196JV - automotive 4 production datasheet 3.0 electrical characteristics 3.1 dc characteristics absolute maximum ratings* storage temperature C60c to +150c voltage from v pp or ea# to v ss or angnd ............................... C0.5 v to +13.0 v voltage from any other pin to v ss or angnd ............................... C0.5 v to +7.0 v this includes v pp on rom and cpu devices. power dissipation................................. 0.5 w operating conditions t a (ambient temperature under bias) .... C40c to +125c v cc (digital supply voltage) 4.75 v to 5.25 v v ref (analog supply voltage) 4.75 v to 5.25 v f osc (oscillator frequency ..................... 4 mhz to 20 mhz notice: this is a production data sheet. the specifi- cations are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. *warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. note: angnd and v ss should be nominally at the same potential. table 2. dc characteristics (under listed operating conditions) (sheet 1 of 2) sym parameter min typ max units test conditions i cc v cc supply current (C40c to +125c ambient) 95 ma xtal1 = 20 mhz v cc = v pp = v ref = 5.25 v (while device in reset) i cc1 active mode supply current (typical) 60 ma i ref a/d reference supply current 25ma i idle idle mode current 15 40 ma xtal1 = 20 mhz v cc = v pp = v ref = 5.25 v i pd powerdown mode current 50 a v cc = v pp = v ref = 5.25 v (note 5) v il input low voltage (all pins) C0.5 0.3 v cc v v ih input high voltage (all pins) 0.7 v cc v cc + 0.5 v (note 6) v ol output low voltage (outputs configured as push/pull) 0.3 0.45 1.5 v i ol = 200 a (3) i ol = 3.2 ma i ol = 7.0 ma notes: 1. all bd (bidirectional) pins except clkout. clkout is excluded due to not being weakly pulled high in reset. bd pins include port1, port2, ports 3, 4 and 5 and port6. 2. standard input pins include xtal1, ea#, reset# and port 1/2/3/4/5/6 when configured as inputs. 3. all bidirectional i/o pins when configured as outputs (push/pull). 4. device is static and should operate below 1 hz, but only tested down to 4 mhz. 5. typicals are based on limited number of samples and are not guaranteed. the values listed are at room temperature and v ref = v cc = 5.0 v. 6. v ih max for port 0 pins = v ref + 0.5 v. 7. this specification is not tested in production and is based upon theoretical estimates and/or product characterization.
production datasheet 5 87C196JV - automotive v oh output high voltage (output configured as push/pull) v cc C 0.3 v cc C 0.7 v cc C 1.5 v i oh = C200 a (3) i oh = C3.2 ma i oh = C7.0 ma i li input leakage current (standard inputs p3/4) 10 a v ss v in v cc (2) i li1 input leakage current (port 0a/d inputs) 2 a v ss v in v ref i ih input high current (nmi pin) 175 a v ss v in v cc v oh2 output high voltage in reset v cc C 1 v i oh = C15 a (1) i oh2 output high current in reset C30 C75 C90 C120 C240 C280 a v oh2 = v cc C 1 v (7) v oh2 = v cc C 2.5 v v oh2 = v cc C 4 v v ol3 output low voltage in reset (reset pin only) 0.3 0.5 0.8 v i ol3 = 4 ma (7) i ol3 = 6 ma i ol3 = 8 ma r rst reset pullup resistor 6k 65k w c s pin capacitance (any pin to v ss ) 10 pf f test = 1.0 mhz (5) r wpu weak pullup resistance (approximate) 150k w (5) table 2. dc characteristics (under listed operating conditions) (sheet 2 of 2) sym parameter min typ max units test conditions notes: 1. all bd (bidirectional) pins except clkout. clkout is excluded due to not being weakly pulled high in reset. bd pins include port1, port2, ports 3, 4 and 5 and port6. 2. standard input pins include xtal1, ea#, reset# and port 1/2/3/4/5/6 when configured as inputs. 3. all bidirectional i/o pins when configured as outputs (push/pull). 4. device is static and should operate below 1 hz, but only tested down to 4 mhz. 5. typicals are based on limited number of samples and are not guaranteed. the values listed are at room temperature and v ref = v cc = 5.0 v. 6. v ih max for port 0 pins = v ref + 0.5 v. 7. this specification is not tested in production and is based upon theoretical estimates and/or product characterization.
87C196JV - automotive 6 production datasheet 3.2 ac characteristics 3.2.1 test conditions ? capacitive load on all pins = 100 pf ? rise and fall times = 10 ns ? f osc = 20 mhz table 3. ac characteristics (over specified operating conditions) (sheet 1 of 2) symbol parameter min max units the system must meet these specifications to work with the 87C196JV - automotive t avdv address valid to input data valid 3t osc C 55 ns t rldv rd# active to input data valid t osc C 25 ns t cldv clkout low to input data valid t osc C 50 ns t rhdz end of rd# to input data float t osc ns t rxdx data hold after rd# inactive 0 ns the 87C196JV - automotive will meet these specifications f xtal oscillator frequency 4 20 mhz (1) t osc oscillator period (1/f xtal ) 50 250 ns t xhch xtal1 high to clkout high or low 20 110 ns (2) t clcl clkout period 2t osc ns (2) t chcl clkout high period t osc C10 t osc +15 ns t cllh clkout falling edge to ale rising C10 15 ns t llch ale/adv# falling edge to clkout rising C20 15 ns t lhlh ale/adv# cycle time 4t osc ns (2) t lhll ale/adv# high period t osc C10 t osc +10 ns t avll address setup to ale/adv# falling edge t osc C15 ns t llax address hold after ale/adv# falling edge t osc C40 ns t llrl ale/adv# falling edge to rd# falling edge t osc C30 ns t rlcl rd# low to clkout falling edge 430 ns t rlrh rd# low period t osc C5 ns t rhlh rd# rising edge to ale/adv# rising edge t osc t osc +25 ns (3) t rlaz rd# low to address float 5 ns (5) notes: 1. testing performed at 4 mhz, however, the device is static by design and will typically operate below 1 hz. 2. typical specifications, not guaranteed. 3. assuming back-to-back bus cycles. 4. 8-bit bus only. 5. t rlaz (max) = 5 ns by design.
production datasheet 7 87C196JV - automotive t llwl ale/adv# falling edge to wr# falling edge t osc C10 ns t clwl clkout low to wr# falling edge C5 25 ns t qvwh data stable to wr# rising edge t osc C23 ns t chwh clkout high to wr# rising edge C10 15 ns t wlwh wr# low period t osc C20 ns t whqx data hold after wr# rising edge t osc C25 ns t whlh wr# rising edge to ale/adv# rising edge t osc C10 t osc +15 ns (3) t whax ad8-15 hold after wr# rising edge t osc C30 ns (4) t rhax ad8-15 hold after rd# rising edge t osc C30 ns (4) figure 4. system bus timing table 3. ac characteristics (over specified operating conditions) (sheet 2 of 2) symbol parameter min max units notes: 1. testing performed at 4 mhz, however, the device is static by design and will typically operate below 1 hz. 2. typical specifications, not guaranteed. 3. assuming back-to-back bus cycles. 4. 8-bit bus only. 5. t rlaz (max) = 5 ns by design. a5864-01 xtal1 clkout ale rd# wr# bhe# t osc t xhch t chcl t clcl t clch t llch t lhlh t lhll t llrl t rlrh t rhlh t rhdz t avll t llax t rldv address out data in t avdv t llwl t wlwh t whlh t qvwh t whqx data out address out address out valid address out t whax , t rhax t rlaz bus bus ad15:8
87C196JV - automotive 8 production datasheet table 4. external clock drive symbol parameter min max units 1/t xlxl oscillator frequency 420mhz t xlxl oscillator period (t osc ) 50 250 ns t xhxx high time 0.35t osc 0.65t osc ns t xlxx low time 0.35t osc 0.65t osc ns t xlxh rise time 10 ns t xhxl fall time 10 ns figure 5. external clock drive waveforms figure 6. input/output test conditions t xlxx a2119-03 t xhxx t xhxl t xlxl 0.3 v cc C 0.5 v 0.7 v cc + 0.5 v t xlxh 0.7 v cc + 0.5 v 0.3 v cc C 0.5 v xtal1 test points 2.0 v 0.8 v note: ac testing inputs are driven at 3.5 v for a logic 1 and 0.45 v for a logic 0. timing measurements are made at 2.0 v for a logic 1 and 0.8 v for a logic 0. 3.5 v 0.45 v a2120-04 2.0 v 0.8 v
production datasheet 9 87C196JV - automotive 3.2.2 explanation of ac symbols each symbol is two pairs of letters prefixed by t for time. the characters in a pair indicate a signal and its condition, respectively. symbols represent the time between the two signal/condition points. figure 7. float test conditions table 5. thermal characteristics device and package q ja q jc an87C196JV - automotive (52-lead plcc) 42c/w 15c/w notes: 1. q ja = thermal resistance between junction and the surrounding environment (ambient). measurements are taken 1 ft. away from case in air flow environment. q jc = thermal resistance between junction and package surface (case). 2. all values of q ja and q jc may fluctuate depending on the environment (with or without airflow, and how much airflow) and device power dissipation at temperature of operation. typical variations are 2c/w. 3. values listed are at a maximum power dissipation of 0.5 w. v load v load C 0.15 v v load + 0.15 v timing reference points v oh C 0.15 v v ol + 0.15 v note: for timing purposes, a port pin is no longer floating when a 150 mv change from load voltage occurs and begins to float when a 150 mv change from the loading v oh /v ol level occurs with i ol /i oh 15 ma. a2121-03 table 6. explanation of ac symbols conditions signals h C high a C address ha C hlda# l C low b C bhe# l C ale/adv# v C valid c C clkout r C rd# x C no longer valid d C data w C wr#/wrh#/wri# z C floating g C buswidth x C xtal1 y C ready
87C196JV - automotive 10 production datasheet 3.3 eprom specifications 3.3.1 ac eprom programming characteristics operating conditions: ? load capacitance = 150 pf ?t c = 25c 5c ?v ref = 5 v 0.25 v ?v ss = 0 v ? angnd = 0 v ?v pp = 12.5 v 0.25 v ? ea# = 12.5 v 0.25 v ?f osc = 5 mhz ?v cc = 5 v 0.25 v table 7. ac eprom programming characteristics symbol parameter min max units t avll address setup time 0 t osc t llax address hold time 100 t osc t dvpl data setup time 0 t osc t pldx data hold time 400 t osc t lllh pale# pulse width 50 t osc t plph prog# pulse width (3) 50 t osc t lhpl pale# high to prog# low 220 t osc t phll prog# high to next pale# low 220 t osc t phdx word dump hold time 50 t osc t phpl prog# high to next prog# low 220 t osc t lhpl pale# high to prog# low 220 t osc t pldv prog# low to word dump valid 50 t osc t shll reset# high to first pale# low 1100 t osc t phil prog# high to ainc# low 0 t osc t ilih ainc# pulse width 240 t osc t ilvh pver hold after ainc# low 50 t osc t ilpl ainc# low to prog# low 170 t osc t phvl prog# high to pver# valid 220 t osc notes: 1. run time programming is done with f osc = 6 mhz to 10 mhz, v cc , v pd , v ref = 5 v 0.25 v, t c = 25c 5c and v pp = 12.5 v 0.25 v. for run-time programming over a full operating range, contact factory. 2. programming specifications are not tested, but guaranteed by design. this specification is for the word dump mode. for programming pulses use 300t osc + 100 s. table 8. dc eprom programming characteristics symbol parameter min max units i pp v pp programming supply current 100 ma note: v pp must be within 1 v of v cc while v cc < 4.5 v. v pp must not have a low impedance path to ground or v ss while v cc > 4.5 v.
production datasheet 11 87C196JV - automotive 3.3.2 eprom programming waveforms figure 8. slave programming mode data program mode with single program pulse figure 9. slave programming mode in word dump or data verify mode with auto increment ports 3/4 reset# address/command t avll data address/command t shll t lllh t dvpl t pldx prog# p2.2 pale# p2.1 t lhpl t plph t llax t phll pver# p2.0 t phvl valid t llvh a5838-01 ports 3/4 reset# address/command ver bits/wd dump t shll prog# p2.2 pale# p2.1 t pldv pver# p2.0 t ilpl addr addr + 2 t phdx t pldv t phdx ver bits/wd dump t a5839-01 phpl
87C196JV - automotive 12 production datasheet 3.4 a/d converter specifications the speed of the a/d converter in the 10-bit or 8-bit modes can be adjusted by setting the ad_time special function register to the appropriate value. the ad_time register only programs the speed at which the conversions are performed, not the speed at which it can convert correctly. the converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of v ref . v ref must be within 0.5 v of v cc since it supplies both the resistor ladder and the digital portion of the converter and input port pins. for testing purposes, after a conversion is started, the device is placed in the idle mode until the conversion is complete. testing is performed at v ref = 5.12 v and 20 mhz operating frequency. there is an ad_test register that allows for conversion on angnd and v ref as well as zero offset adjustment. the absolute error listed is without doing any adjustments. figure 10. slave programming mode timing in data program mode with repeated program pulse and auto increment ports 3/4 reset# address/command data prog# p2.2 pale# p2.1 t phpl pver# p2.0 t phil data p1 p2 valid for p1 t ilpl valid for p2 t ilvh t ilih ainc# p2.4 a5840-01 table 9. a/d operating conditions symbol parameter min max units t a automotive ambient temperature C40 +125 c v cc digital supply voltage 4.75 5.25 v v ref analog supply voltage 4.75 5.25 v (2,3) t sam sample time 2.0 s (4) t conv conversion time 15 18 s (4) f osc oscillator frequency 4 20 mhz notes: 1. angnd and v ss should nominally be at the same potential. 2. v ref must not exceed v cc by more than +0.5 v. 3. testing is performed at v ref = 5.12 v. 4. the value of ad_time must be selected to meet these specifications.
production datasheet 13 87C196JV - automotive table 10. a/d characteristics parameter typical*(1) min max units** notes resolution 1024 10 1024 10 levels bits absolute error 0 3 lsbs full-scale error 2 lsbs zero offset error 2 lsbs non-linearity 3 lsbs differential non-linearity > C 0.5 + 0.5 lsbs channel-to-channel matching 0 1 lsbs repeatability 0.25 0 lsbs (1) temperature coefficients: offset fullscale differential non-linearity 0.009 lsb/c (1) off isolation C 60 db (1,2,3) feedthrough C 60 db (1,2) v cc power supply rejection C 60 db (1,2) input resistance 750 1.2 k w (4) dc input leakage C 2 0 2 a notes: *these values are expected for most parts at 25c but are not tested or guaranteed. **an lsb, as used here, has a value of approximately 5 mv. (see automotive handbook for a/d glossary of terms). 1. these values are not tested in production and are based on theoretical estimates and/or laboratory test. 2. dc to 100 khz 3. multiplexer break-before-make guaranteed. 4. resistance from device pin, through internal mux, to sample capacitor.
87C196JV - automotive 14 production datasheet 3.5 ac characteristics - serial port - shift register mode operating conditions: ? t a = C40c +125c ? v ss = 0.0 v ? v cc = 5.0 v 5% ? load capacitance = 100 pf table 11. serial port timing - shift register mode symbol parameter min max units t xlxl serial port clock period 8t osc ns t xlxh serial port clock falling edge to rising edge 4t osc C 50 4t osc + 50 ns t qvxh output data setup to clock rising edge 3t osc ns t xhqx output data hold after clock rising edge 2t osc C 50 ns t xhqv next output data valid after clock rising edge 2t osc + 50 ns t dvxh input data setup to clock rising edge 2t osc + 200 ns t xhdx input data hold after clock rising edge 0 ns t xhqz last clock rising to output float 5t osc ns note: 1. parameters not tested. figure 11. waveform - serial port - shift register mode 0 a2080-03 valid valid valid valid valid valid valid valid rxd x (in) txd x 01 2 3 4 5 6 7 t qvxh t xlxl t dvxh t xhqv t xhqz t xhdx t xhqx t xlxh rxd x (out)
production datasheet 15 87C196JV - automotive 3.5.1 52-lead device design considerations the 87C196JV - automotive a-step is a memory scalar of the 52-lead 87c196jt a-step designed for strict functional and electrical compatibility. both the 87C196JV - automotive and 87c196jt are 52-lead members of the kx product family. some functions that are on 68-lead devices are not supported on 52-lead devices because of the reduced pin-count. following are the functionality differences between 52-lead kx family members and 68-lead kx family members. 68-lead functions unsupported on the 52-lead 87C196JV - automotive : the following is a list of recommended practices when using 52-lead kx devices: 1. external memory . use an 8-bit bus mode only. there is neither a wrh# or buswidth pin. the bus cannot dynamically switch from 8- to 16-bit or vice versa. set the ccb bytes to an 8-bit only mode, using wr# function only. 2. wait state control . use the ccb bytes to configure the maximum number of wait states. if the ready pin is selected to be a system function, the device locks up waiting for ready. if the ready pin is configured as lsio (default after reset#), the internal logic receives a logic 0 level and insert the ccb defined number of wait states in the bus cycle. don't use irc = 111. 3. nmi support . the nmi is not bonded out. make the nmi vector at location 203eh vector to a return instruction. this is for glitch safety protection only. 4. auto-programming mode . the 52-lead device only supports the 16-bit zero wait state bus during auto-programming. 5. epa4 through epa7 . since the jt/jr/jq devices use the kr silicon, these functions are in the device, just not bonded out. a programmer can use these as compare only channels or for other functions like software timer, start and a/d conversion, or reset timers. 6. slave port support . the slave port can not be used on 52-lead devices due to p5.4/slpint and p5.1/slpcs not being bonded-out. 7. port functions . some port pins have been removed. p5.7, p5.6, p5.5, p5.1, p6.2, p6.3, p1.4 through p1.7, p2.3, p2.5, p0.0 and p0.1. the pxreg, pxssel, and pxio registers can still be updated and read. the programmer should not use the corresponding bits associated with the removed port pins to conditionally branch in software. treat these bits as reserved. additionally, these port pins should be setup internally by software as follows: ? written to pxreg as 1 or 0 ? configured as push/pull, pxio as 0 ? configured as lsio this configuration effectively straps the pin either high or low. do not configure as open drain output 1, or as an input pin. this device is cmos . 8. epa timer reset/write conflict . if the user writes to the epa timer at the same time that the timer is reset, it is indeterminate which takes precedence. users should not write to a timer if using epa signals to reset it. ? analog channels 0 and 1 ? inst pin functionality ? slpint and slpcs pin support ? hld/hlda functionality ? external clocking/direction of timer1 ? wrh or bhe functions ? dynamic buswidth ? dynamic wait state control
87C196JV - automotive 16 production datasheet 9. valid time matches . the timer must increment/decrement to the compare value for a match to occur. a match does not occur if the timer is loaded with a value equal to an epa compare value. matches also do not occur if a timer is reset and 0 is the epa compare value. 10. p6_pin.4C.7 not updated immediately . values written to p6_reg are temporarily held in a buffer. if p6_mode is cleared, the buffer is loaded into p6_reg.x. if p6_mode is set, the value stays in the buffer and is loaded into p6_reg.x when p6_mode.x is cleared. since reading p6_reg returns the current value in p6_reg and not the buffer, changes to p6_reg cannot be read until/unless p6_mode.x is cleared. 11. write cycle during reset . if reset occurs during a write cycle, the contents of the external memory device may be corrupted. 12. i ndirect shift instruction . the upper 3 bits of the byte register holding the shift count are not masked completely. if the shift count register has the value 32 x n, where n = 1, 3, 5, or 7, the operand shifts 32 times. this should have resulted in no shift taking place. 13. p2.7 (clkout). p2.7 (clkout) does not operate in open drain mode . on the 87C196JV - automotive clkout is active during reset. 3.5.2 87C196JV - automotive errata executing routines in the users rom while the device is operating in serial programming mode problem: all code fetches above the first 8k bytes of user rom while the device is operating in serial port programming mode will be directed to external memory. therefore, if the user wants to call any routines in the user rom, the entire routine must be within the first 8k bytes of memory (0a000 C 0bfffh in serial port programming mode). for example, if the rism go command is used with a target address of 0c000h, the device will attempt to fetch code from external memory rather than the on-board rom. implication: this errata only affects code fetches from the user rom. data fetches to the entire rom work correctly. it is not possible to execute code from above the first 8k byte of user rom while the device is operating in serial port programming mode. workaround: none. status: nofix . refer to summary table of changes to determine affected stepping(s). 3.5.3 87c196jr/jq d-step to 87C196JV - automotive a-step design considerations 1. memory scalar the 87C196JV - automotive a-step is a memory scalar of the 87c196jr d-step. 2. 1b00C1bdfh external addressing the 87c196jr/jq d-step cannot access external memory locations 1b00h-1bdfh. this jr/jq d-step errata has been corrected on the 87C196JV - automotive a-step. a bus cycle does not occur when these addresses are accessed. if attempting to read from 1b00h-1bdfh a value of ffh is returned even though a read cycle is not generated. writing to these locations will not generate an external bus cycle either. 87c196jr d-step 87C196JV - automotive a-step register ram 18h to 1ffh 18h to 3ffh and 1c00h to 1dffh internal (code) ram 400h to 4ffh 400h to 5ffh internal rom/eprom 2000h to 5fffh 2000h to dfffh
production datasheet 17 87C196JV - automotive 3.5.4 87c196jr/jq c-step to jv a-step design considerations this section documents differences between the 87c196jr c-step (jr-c) and the 87C196JV - automotive a-step (jv-a). for a list of design considerations between 68-lead and 52-lead devices, please refer to the 52-lead device design considerations section of this data sheet. since the 87c196jq is simply a memory scalar of the 87c196jr, the term jr in this section refers to both the jr and jq versions of the device unless otherwise noted. the jr-c is simply a 87c196kr c-step (kr-c) device packaged within a 52-lead package. this reduction in pin count necessitated not bonding-out certain pins of the kr-c device. the fact that these removed pins were still present on the device but not available to the outside world allowed the programmer to take advantage of some of the 68-lead kr features. the jv-a is a fully-optimized 52-lead device based on the 87c196jt a-step device which is based on the jr-d step device. the jt-a design data base was used to assure that the jv-a would be fully compatible with the kr-c, jr-c, jr-d and other kx family members. the main difference between the jv-a and the jt-a as compared to the jr-c is that several of the unused (not bonded-out) functions on the jr-c were removed altogether on the jt-a. following is a list of differences between the jr-c and the jv-a, jt-a: 1. port 3 push-pull operation it was discovered on jr-c that if port 3 is selected for push-pull operation (p34_drv register) during low speed i/o (lsio), the port was driving data when the system bus was attempting to input data. it is rather unlikely that this errata would affect an application because the application would have to use port 3 for both lsio and as an external addr/data bus. none the less, this errata was corrected on the jt-a and jv-a. 2. v oh2 strengthene d the dc characteristics section of the automotive kr data sheet contains a parameter, v oh2 (output high voltage in reset (bd ports)) which is specified at v cc C 1 v min at i oh2 = C15 ma. this specification indicates the strength of the internal weak pull-ups that are active during and after reset. these weak pull-ups stay active until the user writes to pxmode (previously known as pxssel) and configures the port pin as desired. these pull-ups do not meet this v oh2 spec on the jr-c. the weak pull-ups on specified jt-a and jv-a ports have been enhanced to meet the published specification of i oh2 = C15 a. 3. once mod e once mode is entered by holding a single pin low on the rising edge of reset#. on the kr, this pin is p5.4/slpint. the jr-c does not support once mode since p5.4/slpint (once mode entry pin) is not bonded-out on these devices. to provide once mode on the jt-a and jv-a, the once mode entry function was moved from p5.4/slpint to p2.6/hlda. this allows the jt-a and jv-a to enter once mode using p2.6 instead of removed pin p5.4. 4. port0 on the jr-c, p0.0 and p0.1 are not bonded out. however, these inputs are present in the device and reading them provides an indeterminate result. on the jt a-step and jv-a the analog inputs for these two channels at the multiplexer are tied to v ref . therefore, initiating an analog conversion on ach0 or ach1 results in a value equal to full scale (3ffh). on the jt a-step and jv-a the digital inputs for these two channels are tied to ground, therefore reading p0.0 or p0.1 results in a digital ``0''.
87C196JV - automotive 18 production datasheet 5. port1 on the jr-c, p1.4, p1.5, p1.6 and p1.7 are not bonded out but are present internally on the device. this allows the programmer to write to the port registers and clear, set or read the pin even though it is not available to the outside world. however, to maintain compatibility with jt a-step, jv a-step and future devices, it is recommended that the corresponding bits associated with the removed pins not be used to conditionally branch in software. these bits should be treated as reserved. on the jt a-step and jv a-step unused port logic for these four port pins has been removed from the device and is not available to the programmer. corresponding bits in the port registers have been hard-wired to provide the following results when read: 6. port2 on the jr-c, p2.3 and p2.5 are not bonded out but are present internally on the device. this allows the programmer to write to the port registers and clear, set or read the pin even though is not available to the outside world. however, to maintain compatibility with jt a-step, and jv a-step and future devices, it is recommended that the corresponding bits associated with the removed pins not be used to conditionally branch in software. these bits should be treated as reserved. on the jt-a and jv-a, unused port logic for these two port pins has been removed from the device and is not available to the programmer. corresponding bits in the port registers have been hardwired to provide the following results when read: 7. port5 on the jr-c, p5.1, p5.4, p5.5, p5.6 and p5.7 are not bonded out but are present internally on the device. this allows the programmer to write to the port registers and clear, set or read the pin even though it is not available to the outside world. on the jt a-step and jv a-step unused port logic for these five port pins has been removed. the data read from the p5_pin, p5_reg, p5_mode, and p5_dir register bits associated with these removed pins can be unpredictable on these devices due to the removed logic. therefore, these bits should not be used to conditionally branch in software. these bits should be treated as reserved. register bits when read p1_pin.x (x = 4,5,6,7) 1 p1_reg.x (x = 4,5,6,7) 1 p1_dir.x (x = 4,5,6,7) 1 p1_mode.x (x = 4,5,6,7) 0 note: writing to these bits has no effect. register bits when read p2_pin.x (x = 3,5) 1 p2_reg.x (x = 3,5) 1 p2_dir.x (x = 3,5) 1 p2_mode.x (x = 3,5) 0 note: writing to these bits has no effect.
production datasheet 19 87C196JV - automotive 8. port6 on the jr-c, p6.2 and p6.3 are not bonded out but are present internally on the device. this allows the programmer to write to the port registers and clear, set or read the pin even though it is not available to the outside world. however, to maintain compatibility with jt a-step, and jv a-step and future devices, it is recommended that the corresponding bits associated with the removed pins not be used to conditionally branch in software. these bits should be treated as reserved. on the jt a-step and jv a-step, unused port logic for these two port pins has been removed from the device and is not available to the programmer. corresponding bits in the port registers have been hardwired to provide the following results when read: 9. 8xc196jq internal to external memory rollover point 8xc196jq devices are simply 8xc196jr devices with less memory. both the jq-c and jq-d are fabricated from the jr-c and jr-d respectfully. the difference between jq and jr devices is that memory locations beyond the supported boundaries on the jq are not tested in production and should not be used. any software which relies upon reading or writing these locations may not function correctly. following are the supported memory maps for these devices: it is important to note that the internal to external memory roll-over point for both the jr and jq devices is the same (6000h and above goes external). two guidelines the programmer should follow to insure no problems are encountered when using jq devices are: a. for jq devices, the program must contain a jump to a location greater than 5fffh before the 12k boundary (4fffh) is reached. this is necessary only if greater than 12k of program memory is required with a jq device and portions of the program execute from internal rom/eprom. b. for jq devices with ea# tied to ground, use only internal program memory from 2000h to 4fffh. do not use the unsupported locations from 5000h to 5fffh. 10. . epa channels 4 through 7 the jr c-step device is simply a 68-lead kr-c device packaged in a 52-lead package. the reduced pin-out is achieved by not bonding-out the unsupported pins. epa4Cepa7 are among these pins that are not bonded-out. the fact that epa4Cepa7 are still present allows the programmer to use these channels as software timers, to start a/d conversions, reset timers, etc. all of the port pin logic is still present and it is possible to use the epa to toggle these pins internally. please refer to the 52-lead device section in this data sheet for further information. register bits when read p6_pin.x (x = 2,3) 1 p6_reg.x (x = 2,3) 1 p6_dir.x (x = 2,3) 1 p6_mode.x (x = 2,3) 0 note: writing to these bits has no effect. jq c- and d-step jr c- and d-step register ram 18h to 17fh 18h to 1ffh internal (code) ram 400h to 47fh 400h to 4ffh internal rom/eprom 2000h to 4fffh 2000h to 5fffh
87C196JV - automotive 20 production datasheet on the jt a-step and jv a-step the epa4Cepa7 logic has not been removed from the device. this allows the programmer to still use these channels (as on the jr c-step) for software timers, etc. the only difference is that the associated port pin logic has been removed and does not exist internally. to maintain jr c-step to jt a-step and jv a-step compatibility, programmers should make sure that their software does not rely upon the removed port pin logic. 11. . epa overruns epa lock-up can occur if overruns are not handled correctly, refer to intel techbit #db0459 understanding epa capture overruns , date 12-9-93. applies to epa channels with interrupts and overruns enabled (on/rt bit set to 1). 12. . indirect addressing with auto-increment for the special case of a pointer pointing to itself using auto-increment, an incorrect access of the incremented pointer address will occur instead of an access to the original pointer address. all other indirect auto-increment accesses will not be affected. please refer to techbit #mco593. a. incorrect sequence: results in ax being incremented by 1 and the contents of the address pointed to by ax+1 to be loaded into bx. ld ax,#ax ldb bx,[ax]+ b. suggested sequence: results in the contents of the address pointed to by ax to be loaded into bx and ax incremented by 1. ld ax,#bx; where ax does not equal bx ldb cx,[ax]+ 3.5.5 87c196jt to 87C196JV design considerations 1. the additional register ram on the 87C196JV is mapped to 1c00h to 1dffh. on the 87c196jt this memory range is mapped as external memory. 2. the 87C196JV has 48k of eprom located from 2080h to dfffh. the jt has 32k of eprom located from 2080h to 9fffh. memory accesses between 1e00h and ffffh go external for the 87C196JV. access between a000h to ffffh go external for the 87c196jt.
production datasheet 21 87C196JV - automotive 3.5.6 memory map for jv dfffh eprom (internal) 48 kbyte. 2080h user eprom starts here. jv/jt and all kx products same. 207fh chip configuration bytes, pts vectors, interrupt vectors, security key. 2000h jv/jt and all kx products same. (see kx user's manual table 3.2). 1fffh 1f00h internal special function registers (sfr's) (16-bit addressable) jv identical to jt and rest of kx family. jv/jt ` reserved' locations (see figure 3.2 kx user's manual). 1effh mapped as external memory on jv, jt, and rest of kx family. 1e00h 1dffh 1c00h additional register ram on jv. 1bffh external memory space on jv/jt and rest of kx family. 0600h 05ffh 0400h code ram. same on jv, jt, kt. 03ffh 0018h register ram. same on jv, jt, kt. 0017h core special function registers. same on jv, jt, and rest of kx/jx family. 0000h
87C196JV - automotive 22 production datasheet 4.0 datasheet revision history this is the (-004) version of the 8xc196jv 20 mhz datasheet. item revision template converted to new template. editing corrected spelling and grammar errors. product features combined product features on cover page with old cpu and peripheral features sections. section 1.0, introduction on page 1 combined old cover page text and old architecture section into new introduction section. section 1.0, introduction on page 1 first paragraph - changed (jt.-d) to (jt-a). second paragraph - changed: ?<5 m s at 20 mhz to 15 m s at 20mhz ? 200 ns to 250 ns. section 3.0, electrical characteristics on page 4 operating conditions: changed v cc and v ref from 4.5 v to 5.5 v to 4.75 v to 5.25 v. table 2 dc characteristics (under listed operating conditions) on page 4 i cc , i cc1 , i ref - test conditions - changed 5.5 v to 5.25 v. i idle - test conditions - changed 5.5 v to 5.25 v. i pd : ? max - deleted tbd ? test conditions - changed 5.5v to 5.25v; note 6 to note 5. v ih - test conditions - changed note 7 to note 6 v ol and v oh - test conditions - deleted note 5. v ol3 - test conditions - changed note 8 to note 7. rwpu: ? min - deleted 9 ? test conditions - changed note 6 to note 5. note 5 deleted figure 6 input/output test conditions on page 8 added output to title. figure 7 float test conditions on page 9 changed output to float in title. section 3.3.1, ac eprom programming characteristics on page 10 operating conditions - changed v ref ... o.5 v to v ref ... 0.25 v. table 7 ac eprom programming characteristics on page 10 note 1: changed v ref ... o.5 v to v ref ... 0.25 v. table 9 a/d operating conditions on page 12 removed (1) from table heading. v cc and v cc : ? min - changed 4.5 to4.75 ? max - changed 5.5 to 5.25 section 3.2, ac characteristics on page 6 operating conditions: changed v cc ... 10% to v cc ... 5%. section 3.5.2, 87C196JV - automotive errata on page 16 added errata from specification update. section 3.5.4, 87c196jr/jq c-step to jv a-step design considerations on page 17 #7 - port5 - revised with specification update section. section 4.0, datasheet revision history on page 22 updated with revision changes.

▲Up To Search▲

Price & Availability of 87C196JV

	To Download 87C196JV Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .